The present invention relates to an apparatus and method for testing semiconductor electrical devices, particularly memory devices.
Testing is performed on semiconductor devices to locate defects and failures in such devices, typically occurring during the manufacture of the semiconductor devices. As circuit density on semiconductor devices increases, the number of defects and failures can increase. Semiconductor manufacturers, therefore, have an increasing need to detect defects and failures in semiconductor devices as circuit density increases.
Thus, for quality control of semiconductor devices, semiconductor devices are tested, often before a die containing the semiconductor device is packaged into a chip. A series of probes on a test station electrically contact pads on each die in a wafer to access portions of the individual semiconductor devices on the die. For example, in a semiconductor memory device, the probes contact address pads and data input/output pads to access selected memory cells in the memory device. Typical dynamic random access memory devices (xe2x80x9cDRAMxe2x80x9d) include one or more arrays of memory cells that are each arranged in rows and columns. Each array of memory cells includes word or row lines that select memory cells along a selected row, and bit or column lines (or pairs of lines) that select individual memory cells along a row to read data from, or write data to, the cells in the selected row.
During testing, predetermined data values are typically written to selected row and column addresses that correspond to certain memory cells, and then the voltage values are read from those memory cells to determine if the data read matches the data written to those addresses. If the read data does not match the written data, then the memory cells at the selected addresses likely contain defects and the semiconductor device fails the test.
Nearly all semiconductor devices, particularly memory devices, include redundant circuitry on the semiconductor device that can be employed to replace malfunctioning circuits found during testing. By enabling such redundant circuitry, the device need not be discarded even if it fails a particular test. For example, memory devices typically employ redundant rows and columns of memory cells so that if a memory cell in a column or row of the primary memory array is defective, then an entire column or row of redundant memory cells can be substituted therefor, respectively.
Substitution of one of the spare rows or columns is conventionally accomplished by opening a specific combination of fuses (or closing antifuses) in one of several fuse banks on the die. Conventional fuses include polysilicon fuses which can be opened by a laser beam, and also avalanche-type fuses and antifuses. If a given row or column in the array contains a defective memory cell, then the wafer can be moved to another station where a laser blows a fuse to enable a redundant row or column.
The laser blows a selected combination of fuses to provide an address equal to the address of the defective cell. For example, if the defective cell has an eight-bit binary address of 11011011, then the laser blows the third and sixth fuses in a set of eight fuses within one of several fuse banks, thereby storing this address. A compare circuit compares each incoming address to the blown fuse addresses stored in the fuse banks to determine whether the incoming address matches with one of the blown fuse addresses. If the compare circuit determines a match, then it outputs a match signal (typically one bit) to a controller or xe2x80x9cphase generatorxe2x80x9d in a row or column decoder for the memory device. In response thereto, the row or column decoder causes the appropriate redundant row/column to be accessed for data transfer, and ignores the defective row or column in the primary memory array.
The rows and columns of redundant memory cells necessarily occupy space on the die. Moreover, the compare circuitry necessary for accessing the redundant row or column requires space on the die. Compare circuits typically employ multiple exclusive OR gates which require a greater amount of area than other logic gates such as NAND and NOR gates. At least one compare circuit is required for each bank of fuses.
Furthermore, fuses/antifuses and compare circuits are typically located at the periphery of the primary memory array. As a result, lines must be routed from the compare circuits to the redundant rows and columns. These additional lines further take up area on the die. If the compare circuits and fuses were located adjacent to their respective redundant rows or columns, the complexity of the layout of the memory device will increase, which is undesirable.
Semiconductor circuit designers strive to provide greater circuit density on a die of a given size. The die size is typically a size standardized by the semiconductor industry. By providing additional circuitry on a given die, the product incorporating the die is able to provide enhanced or superior performance over competing products in the marketplace. Therefore, there is a need to reduce the area on the die required for redundant rows and columns.
Semiconductor circuit designers have attempted to reduce the number of redundant rows and columns (and their associated circuitry and lines), and thereby free up precious area on the die for additional circuitry to enhance the performance or functionality of the circuitry on the die. However, by so reducing the number of redundant rows and columns, an insufficient number of redundant rows and columns may exist, so that the entire die must be discarded.
An additional problem with reducing the number of redundant memory elements relates to dividing the primary memory array into sub-arrays. Current memory devices divide the primary array of memory cells into sub-arrays so that only a portion of the memory need be energized in a given access, resulting in significant power reduction. Each sub-array requires its own redundant rows and columns. By dividing the memory array into two sub-arrays or xe2x80x9cplanes,xe2x80x9d the redundant rows and columns in the first plane can be substituted for any defective row or column in the primary rows/columns of memory cells in the first plane. Although the memory array could be further divided into a greater number of planes (e.g., four) to further reduce power consumption, then an even fewer number of redundant rows and columns can be employed to replace defective rows and columns in one-fourth of the primary memory array. If a greater number of errors occurred within one quarter of the memory array, then an insufficient number of redundant rows/columns will be available to compensate for such defects. Alternatively, no planes could be employed so that all of the redundant rows and columns can be used to replace defective rows and columns throughout the memory anywhere throughout the memory array. However, such a scheme requires a greater number of routing lines as compared to dividing the array into two planes.
One known 1-megabitxc3x974 DRAM device, manufactured by Micron Technology, employs a 2:1 multiplexer to selectively couple a row address fuse bank and a column address fuse bank with one compare circuit. Row addresses and column addresses are typically compared by compare circuits to column and row fuse addresses at different times during read/write cycles in a semiconductor memory device. As a result, at no time will the compare circuit be required to compare an address to both a column address stored in one fuse bank and a row address stored in another fuse bank. Consequently, this known 1-megabitxc3x974 DRAM device employs one compare circuit for every two fuse banks by employing a 2:1 multiplexer. Since 2:1 multiplexers employ, at a minimum, two pass gates, while compare circuits employ exclusive OR gates, 2:1 multiplexers require substantially less die area than compare circuits. Therefore, by reducing the number of compare circuits, this prior 1-megabitxc3x974 DRAM device reduces the area on a die. However, there is still a need to further reduce the area on the die.
Semiconductor circuit designers have attempted to reduce the overall number of redundant rows/columns to thereby increase die area by experimenting with improved manufacturing techniques to reduce the number of defects on such dies, to thereby afford them the ability to reduce the number of redundant rows and columns necessary to compensate for defects. However, as circuit densities increase, defects tend to increase, despite the best improvements in manufacturing techniques.
The present invention further reduces the area on a die required for rows and columns of redundant memory cells by sharing compare circuitry with banks of redundant memory cells based on division of the primary memory array into two or more xe2x80x9cplanes.xe2x80x9d Pass gates or multiplexers coupled between at least two banks of fuses and one compare circuit selectively couple the appropriate fuse bank to the compare circuit. Preferably, a bit in the address (e.g., address bit RA9 in a row address word having address bits A0-A10 is received by and controls the multiplexer to select between the two banks of fuses. As a result, only one compare circuit is required for two fuse banks for a redundant row and a redundant column, and also for a pair of redundant row and columns for each plane.
Additionally, the present invention reduces the number of lines coupled between the compare circuits and the rows and columns of redundant memory elements in the memory array. The present invention maps or assigns groups or planes of memory elements into preferably one of two planes. The planes span between blocks of memory in the memory array, where each block is divided by shared sense amplifiers. As a result, while eight lines are coupled to 16 rows or columns, only eight rows or columns will be active at any one time because isolation gates will enable only eight of the 16 rows or columns within two planes of memory. Consequently, the present invention saves on the number of lines required to intercouple the compare circuits to the redundant rows/columns, thereby realizing increased area on the chip for additional circuitry. Additionally, at no time will both blocks of memory on opposite sides of the shared sense amplifier ever be simultaneously energized. Even with the most compressed address testing, no rows or columns on opposite sides of shared sense amplifiers will be energized. Therefore, the layout of memory cells under the present invention will not interfere with even the most compressed address mode testing of the semiconductor memory device.
In a broad sense, the present invention embodies a semiconductor device having a plurality of primary and redundant circuit elements, control and addressing circuitry, at least first and second sets of fuse banks, and a number of electrically conductive intercoupling lines. The plurality of primary circuit elements are addressable by electrically conductive row and column lines based on an external address word having a predetermined bit length. The plurality of primary and redundant circuit elements are divided into at least first and second sets, wherein circuit elements in the first and second sets are not simultaneously active. The first set of redundant elements can substitute for defective circuit elements in the first set of primary circuit elements, and the second set of redundant circuit elements can substitute for defective circuit elements in the second set of primary circuit elements. The redundant circuit elements are divided into at least a plurality of columns.
The control and addressing circuitry is coupled to the electrically conductive row and column lines and permits communication with a plurality of primary circuit elements based on the external address word supplied thereto. The first and second sets of fuse banks store addresses of defective circuit elements in the first and second sets of primary circuit elements, respectively. The number of electrically conductive intercoupling lines is equal to a number of columns of redundant circuit elements in the first set of redundant circuit elements. The intercoupling lines are coupled to the first and second sets of fuse banks and to both the first and second sets of redundant circuit elements.
The present invention also embodies a semiconductor device including a plurality of primary and redundant circuit elements, control and addressing circuitry, at least first and second sets of fuse banks, at least one comparison circuit, and at least one gating circuit. The plurality of primary circuit elements are addressable by electrically conductive row and column lines based on an external address word having a predetermined bit length. The plurality of primary and redundant circuit elements are divided into at least first and second sets wherein circuit elements in the first and second sets are not simultaneously active. The first and second sets of redundant circuit elements can substitute for defective circuit elements in the first and second sets of primary circuit elements, respectively. The redundant circuit elements are divided into at least a plurality of columns.
The control and addressing circuitry is coupled to the electrically conductive row and column lines, and permit communication with the plurality of primary circuit elements based on the external address word supplied thereto. The first and second sets of fuse banks store addresses of defective circuit elements in the first and second sets of primary circuit elements, respectively. The comparison circuit is coupled to the control and addressing circuit and to the first and second sets of circuit elements. The comparison circuit compares the external address word to the stored addresses in either the first or second fuse banks, and outputs a match signal to access one of the columns of redundant circuit elements if the address word and one of the stored addresses correlate. The gating or multiplexing circuit is coupled between the comparison circuit and the first and second fuse banks. The gating circuit receives at least one bit of the address word and selects, based thereon, one of the first and second fuse banks to couple to the comparison circuit.
The present invention solves problems inherent in the prior art of semiconductor devices by increasing realized substrate area on a die by employing multiplexers or selection circuits to allow at least four banks of fuses to share one compare circuit. Additionally, to further realize increased area savings on the substrate, the memory array is divided into planes separated by shared sense amplifiers so that a number n of lines can be routed from the compare circuits to at least 2xc3x97n number of redundant rows/columns, but where only n number of rows/columns are active at any one time due to appropriate selection by isolation gates in the semiconductor device. Other features and advantages of the present invention will become apparent from studying the following detailed description of the presently preferred embodiment, together with the following drawings.